Our great sponsors
-
WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
When I first built the ZipCPU, I wrote an assembly program to test every CPU instruction. If all tests passed, the CPU would halt and the simulator would detect that as a success. If any test failed, the CPU would go into a busy wait and the simulator would detect that as a failure. One CPU register held within it the number of the current test. I then ran this software on the CPU both normally, and through a single-stepping debug interface. That way I had strong confidence that, once I placed it onto the FPGA, I'd be at least able to use the debugging interface to step the CPU and see the register contents along the way. You can read about what this is like here.
Building on top of that - I could modify my software emulator to produce the same format as the Verilog testbench would produce (thinking back to nestest log), and compare the output from C and Verilog implementations when in doubt.
Related posts
- Five legally free FPGA books (plus one about Machine Learning)
- What make xilinx fpga runs soft core cpu faster than lattice
- Why is simulation such an important step in the design workflow? Why not just run on actual hardware?
- Using Xilinx AXI Datamover to move DDR memory to FPGA block RAM
- Ultraembedded RISCV Module