neorv32-setups
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neorv32-setups | litex | |
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5 | 29 | |
52 | 2,683 | |
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8.6 | 9.7 | |
6 days ago | 3 days ago | |
VHDL | C | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
litex
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FPGA Dev Boards for $150 or Less
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Sunset TCL scripts ?
LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.
- synthesizing and using the Ibex RISC-V core
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Been messing around with litex and migen on my Tang Primer 20K
To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen
- CPU design for college project
- How can I learn about RISC-V and use case? I want to do a project for begginers
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
- LiteX: Build Hardware Easily
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Using FPGAs for computations as a beginner
I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.
What are some alternatives?
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
nmigen-tutorial - A tutorial for using nmigen
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
SpinalHDL - Scala based HDL
fpu - IEEE 754 floating point library in system-verilog and vhdl
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
verilog-ethernet - Verilog Ethernet components for FPGA implementation