neorv32-setups
fpu
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| neorv32-setups | fpu | |
|---|---|---|
| 5 | 1 | |
| 52 | 46 | |
| - | - | |
| 8.6 | 6.1 | |
| 6 days ago | about 2 months ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
fpu
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High level floating point arithmetic in vhdl
Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.
What are some alternatives?
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
fpu-sp - IEEE 754 floating point library in system-verilog and vhdl
litex - Build your hardware, easily!
uart-for-fpga - Simple UART controller for FPGA written in VHDL
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
or1200 - OpenRISC 1200 implementation
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
VHDL-Guide - VHDL Guide