neoTRNG
neorv32
| neoTRNG | neorv32 | |
|---|---|---|
| 10 | 77 | |
| 153 | 1,433 | |
| - | - | |
| 7.3 | 9.9 | |
| about 1 month ago | 1 day ago | |
| VHDL | C | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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neoTRNG
- A really tiny and platform-independent true random number generator for FPGAs and ASICs
- Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
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Synthesizable LFSR counter (feedback 16,13)
This TRNG (VHDL) provides some kind of "imulation mode where the entropy source is replaced by a LFSR. When simulated, the testbench prints the random data to the simulator console. Maybe this can help as starting point.
- A tiny and platform-agnostic TRUE random number generator for any FPGA
- A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- A Tiny and Platform-Independent True Random Number Generator for any FPGA.
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
picoMIPS - picoMIPS processor doing affine transformation
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
serv - SERV - The SErial RISC-V CPU