neoTRNG VS spi-fpga

Compare neoTRNG vs spi-fpga and see what are their differences.

neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). (by stnolting)
Vhdl Fpga trng random-number-generators Random ring-oscillator entropy-source neorv32 Cryptography Entropy Asic asic-design
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spi-fpga

SPI master and SPI slave for FPGA written in VHDL (by jakubcabal)
spi-slave spi-master Fpga Vhdl Spi Controller spi-loopback spi-controller cyc1000 accelerometer ghdl
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neoTRNG spi-fpga
10 2
153 157
- -
7.3 0.0
about 1 month ago about 3 years ago
VHDL VHDL
BSD 3-clause "New" or "Revised" License MIT License
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neoTRNG

Posts with mentions or reviews of neoTRNG. We have used some of these posts to build our list of alternatives and similar projects.

spi-fpga

Posts with mentions or reviews of spi-fpga. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing neoTRNG and spi-fpga you can also consider the following projects:

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

w11 - PDP-11/70 CPU core and SoC

wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

neoTRNG vs neorv32 spi-fpga vs vunit neoTRNG vs neo430 spi-fpga vs catapult-v3-smartnic-re neoTRNG vs neorv32-setups spi-fpga vs upduino-projects neoTRNG vs neorv32-riscof spi-fpga vs w11 spi-fpga vs wb_spi_bridge spi-fpga vs fpga_puf spi-fpga vs AXI4 spi-fpga vs spi-to-axi-bridge