spi-fpga
fpga_puf
spi-fpga | fpga_puf | |
---|---|---|
2 | 2 | |
157 | 87 | |
- | - | |
0.0 | 0.0 | |
about 3 years ago | over 1 year ago | |
VHDL | VHDL | |
MIT License | BSD 3-clause "New" or "Revised" License |
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spi-fpga
-
The accelerometer on the CYC1000 FPGA board.
Last year I did experiments with the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example for my Git repository with SPI controllers. I also started using GHDL in GitHub Actions to automate my simulations. It is an easy-to-use CI for VHDL projects. https://github.com/jakubcabal/spi-fpga
- Does anyone have a Slave Quad SPI in VHDL?
fpga_puf
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipwhisperer - ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
win95-keygen - A product key generator for the now-retired Windows 95 and Windows 98 OS written in Rust
w11 - PDP-11/70 CPU core and SoC
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.