spi-fpga VS spi-to-axi-bridge

Compare spi-fpga vs spi-to-axi-bridge and see what are their differences.

spi-to-axi-bridge

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller. (by airhdl)
InfluxDB - Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com
featured
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com
featured
spi-fpga spi-to-axi-bridge
2 1
157 31
- -
0.0 0.0
about 3 years ago 5 months ago
VHDL VHDL
MIT License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

spi-fpga

Posts with mentions or reviews of spi-fpga. We have used some of these posts to build our list of alternatives and similar projects.

spi-to-axi-bridge

Posts with mentions or reviews of spi-to-axi-bridge. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing spi-fpga and spi-to-axi-bridge you can also consider the following projects:

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

w11 - PDP-11/70 CPU core and SoC

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

fpu - IEEE 754 floating point library in system-verilog and vhdl