VHDL Systemverilog

Open-source VHDL projects categorized as Systemverilog
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Topics: Vhdl Spi Axi4
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VHDL Systemverilog Projects

  • spi-to-axi-bridge

    An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

VHDL Systemverilog related posts

Index

Project Stars
1 spi-to-axi-bridge 31

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