spi-fpga
AXI4
| spi-fpga | AXI4 | |
|---|---|---|
| 2 | 4 | |
| 157 | 103 | |
| - | 5.0% | |
| 0.0 | 7.6 | |
| about 3 years ago | 21 days ago | |
| VHDL | VHDL | |
| MIT License | GNU General Public License v3.0 or later |
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spi-fpga
-
The accelerometer on the CYC1000 FPGA board.
Last year I did experiments with the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example for my Git repository with SPI controllers. I also started using GHDL in GitHub Actions to automate my simulations. It is an easy-to-use CI for VHDL projects. https://github.com/jakubcabal/spi-fpga
- Does anyone have a Slave Quad SPI in VHDL?
AXI4
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
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Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
rust_hdl
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
w11 - PDP-11/70 CPU core and SoC
wb2axip - Bus bridges and other odds and ends
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL