spi-fpga VS wb_spi_bridge

Compare spi-fpga vs wb_spi_bridge and see what are their differences.

wb_spi_bridge

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP). (by stnolting)
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spi-fpga wb_spi_bridge
2 2
157 19
- -
0.0 0.0
about 3 years ago over 2 years ago
VHDL VHDL
MIT License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

spi-fpga

Posts with mentions or reviews of spi-fpga. We have used some of these posts to build our list of alternatives and similar projects.

wb_spi_bridge

Posts with mentions or reviews of wb_spi_bridge. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing spi-fpga and wb_spi_bridge you can also consider the following projects:

vunit - VUnit is a unit testing framework for VHDL/SystemVerilog

spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

sdram-fpga - A FPGA core for a simple SDRAM controller.

w11 - PDP-11/70 CPU core and SoC

neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components