fpga_puf
neorv32-riscof
| fpga_puf | neorv32-riscof | |
|---|---|---|
| 2 | 2 | |
| 87 | 24 | |
| - | - | |
| 0.0 | 9.1 | |
| over 1 year ago | 2 days ago | |
| VHDL | Python | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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fpga_puf
neorv32-riscof
What are some alternatives?
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neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
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riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
chipwhisperer - ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
fpu - IEEE 754 floating point library in system-verilog and vhdl
win95-keygen - A product key generator for the now-retired Windows 95 and Windows 98 OS written in Rust
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
potato - A simple RISC-V processor for use in FPGA designs.