neorv32-riscof VS potato

Compare neorv32-riscof vs potato and see what are their differences.

neorv32-riscof

βœ”οΈPort of RISCOF to check the NEORV32 for RISC-V ISA compatibility. (by stnolting)

potato

A simple RISC-V processor for use in FPGA designs. (by skordal)
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neorv32-riscof potato
2 1
24 245
- -
9.1 0.0
6 days ago over 1 year ago
Python VHDL
BSD 3-clause "New" or "Revised" License BSD 3-clause "New" or "Revised" License
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neorv32-riscof

Posts with mentions or reviews of neorv32-riscof. We have used some of these posts to build our list of alternatives and similar projects.

potato

Posts with mentions or reviews of potato. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing neorv32-riscof and potato you can also consider the following projects:

neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

riscv-debug-dtm - πŸ› JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

fpu - IEEE 754 floating point library in system-verilog and vhdl

neorv32-setups - πŸ“ NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.