meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architecture (by riscv)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
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| meta-riscv | darkriscv | |
|---|---|---|
| 3 | 3 | |
| 330 | 1,882 | |
| 1.2% | 2.8% | |
| 8.2 | 6.3 | |
| 16 days ago | 10 days ago | |
| BitBake | Verilog | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
meta-riscv
Posts with mentions or reviews of meta-riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-11.
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New to embedded
There does exist a Yocto recipe for RISC-V that claims to support both 32 and 64-bit. I haven't used it myself, but your best bet may be spin up a custom Yocto/OE based distro. You can find the source and documentation here: https://github.com/riscv/meta-riscv
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Pine64 August update: RISC and reward
Great news !. We have a yocto port for JH7110 here https://github.com/riscv/meta-riscv/blob/master/conf/machine/visionfive.conf, I will be happy to add a machine conf for pine64, It should be easy enough to start from above as template.
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Support of the Nezha Allwinner D1 - Yocto kirkstone
Remember our blog post about #Nezha board? It is an SBC with a #RISC-V D1 chip onboard. If you have knowledge of #Yocto, from now on you can create a system image using the #meta-riscv layer. For more please refer to our pull request at GitHub repository: https://github.com/riscv/meta-riscv/pull/327
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing meta-riscv and darkriscv you can also consider the following projects:
meta-balena - A collection of Yocto layers used to build balenaOS images
biriscv - 32-bit Superscalar RISC-V CPU
ready-set-yocto - A short, unofficial guide on getting started with Yocto using a Raspberry Pi
XiangShan - Open-source high-performance RISC-V processor
meta-dimitriOS - A BitBake layer for my Linux based projects
riscv - RISC-V CPU Core (RV32IM)
meta-sifive - SiFive OpenEmbedded / Yocto BSP Layer
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
freedom-u-sdk - Freedom U Software Development Kit (FUSDK)
Cores-VeeR-EH1 - VeeR EH1 core
iob-linux
friscv - RISCV CPU implementation in SystemVerilog