friscv
riscv
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friscv | riscv | |
---|---|---|
1 | 2 | |
14 | 1,040 | |
- | - | |
8.4 | 1.8 | |
2 months ago | over 2 years ago | |
Coq | Verilog | |
MIT License | BSD 3-clause "New" or "Revised" License |
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friscv
riscv
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Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
biriscv - 32-bit Superscalar RISC-V CPU
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
zipcpu - A small, light weight, RISC CPU soft core
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
Cores-VeeR-EH1 - VeeR EH1 core
uhd - The USRP™ Hardware Driver Repository