ddr3-controller
riscv
| ddr3-controller | riscv | |
|---|---|---|
| 3 | 2 | |
| 55 | 1,123 | |
| - | - | |
| 0.0 | 1.8 | |
| over 1 year ago | over 2 years ago | |
| Verilog | Verilog | |
| - | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ddr3-controller
-
Best tutorial on DDR protocol
Shameless plug: Take a look at my own design. I also have apaper written about it.
-
Does anybody have a working SDRAM DDR2 Controller for Cyclone III FPGA?
If /u/UseDelicious4662 wants to port some code to their device, they could look at my DDR3 controller for Xilinx 7 Series. It's 1400 lines of code, and it's as simple as I could make it. The PHY is as good as done, even for DDR2. The logic part needs some work to be compatible with an older generation of DDR SDRAM, but overall it should be portable enough. Once that adaptation is done, they "only" need to figure out how to instantiate the Altera counterparts of OSERDES, ISERDES, and IDELAY. https://github.com/someone755/ddr3-controller
- A custom DDR3 controller for the Arty S7-50 board
riscv
-
Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
What are some alternatives?
control_cpu - FPGA setup with memory and Risc V CPU
biriscv - 32-bit Superscalar RISC-V CPU
simple_ddr_ctrl - A (very) simple DDR3 controller for FPGAs
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zipcpu - A small, light weight, RISC CPU soft core
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
uhd - The USRP™ Hardware Driver Repository
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
dpll - A collection of phase locked loop (PLL) related projects