black-parrot
A Linux-capable RISC-V multicore for and by the world (by black-parrot)
neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
| black-parrot | neorv32 | |
|---|---|---|
| 5 | 77 | |
| 531 | 1,429 | |
| 2.6% | - | |
| 8.2 | 9.9 | |
| 9 days ago | 3 days ago | |
| SystemVerilog | C | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
black-parrot
Posts with mentions or reviews of black-parrot.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-10.
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Verilator - Do I need to maintain two testbench suits?
Another option is to have a single verilog testbench with clock and reset ports driven by verilator:https://github.com/black-parrot/black-parrot/blob/master/bp_top/test/tb/bp_tethered/test_bp.cpphttps://github.com/black-parrot/black-parrot/blob/master/bp_top/test/tb/bp_tethered/testbench.sv
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Which FPGA for getting into RISC-V?
It depends drastically on the core and configuration, but a default configured BlackParrot: https://github.com/black-parrot/black-parrot takes up about 50% of Z2 resources without any FPGA-specific tweaks.
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ASIC roundup of open source RISC-V CPU cores
Whoops, read the blog “no sram”. Would love to get my project https://github.com/black-parrot/black-parrot/tree/master on there. Do you have a sense for how many instances your flow could support? We use hardened srams for our caches which are minimally 8kB each at the moment.
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Contribution to Open Source Hardware Projects
What's your background? We have starting projects in a few areas on our RV64 multicore project: https://github.com/black-parrot/black-parrot
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A case for J standard extension?
https://github.com/black-parrot/black-parrot has coherent I$/D$
neorv32
Posts with mentions or reviews of neorv32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
When comparing black-parrot and neorv32 you can also consider the following projects:
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
picoMIPS - picoMIPS processor doing affine transformation
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
serv - SERV - The SErial RISC-V CPU
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip
openFPGALoader - Universal utility for programming FPGA