neorv32 VS openFPGALoader

Compare neorv32 vs openFPGALoader and see what are their differences.

neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
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neorv32 openFPGALoader
77 13
1,415 1,027
- -
9.9 9.2
1 day ago 5 days ago
C C++
BSD 3-clause "New" or "Revised" License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

neorv32

Posts with mentions or reviews of neorv32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.

openFPGALoader

Posts with mentions or reviews of openFPGALoader. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-23.

What are some alternatives?

When comparing neorv32 and openFPGALoader you can also consider the following projects:

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

pcm - Processor Counter Monitor [Moved to: https://github.com/intel/pcm]

linux-on-litex-vexriscv - Linux on LiteX-VexRiscv

XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.

picoMIPS - picoMIPS processor doing affine transformation

pcm - Intel® Performance Counter Monitor (Intel® PCM)

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

prjxray - Documenting the Xilinx 7-series bit-stream format.

chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

XilinxVirtualCable - Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen