neorv32
openFPGALoader
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neorv32 | openFPGALoader | |
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77 | 13 | |
1,415 | 1,027 | |
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9.9 | 9.2 | |
1 day ago | 5 days ago | |
C | C++ | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
openFPGALoader
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STEPS to install ISE 14.7 in DEBIAN 12
Another way to flash the devices in Linux is to use https://github.com/trabucayre/openFPGALoader which supports a variety of cables and devices. It also supports the Xilinx Virtual Cable protocol, which allows you to use Xilinx tools like ChipScope with almost any cable.
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GAO under Linux
Even though I saw multiple proposed solutions around the web, I could not get the Gowin cable to be detected under Ubuntu Linux as well, so neither the programmer nor GAO could work. I tried opensource openFPGALoader as an alternative to the programmer (but not GAO of course..), but got some issues as well (not with cable, but with certain bitstreams causing the programming to hang). So the easiest solution for me to stick with Windows version.
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issue with Gowin 20k and openFPGAloader
i could/should eventually open a ticket on the openFPGAloader indeed
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[Asking for Help] Tang Nano 9K Programmer - Linux Ubuntu 20.04 - "No USB Cable Connection"
Most Linux users seem to prefer openFPGALoader, but if you need GAO and the other suggestions don't work you might have to use a Windows VM, thankfully Gowin IDE supports (supported?) Windows XP/7 if you want a lightweight guest.
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Quartus on Steam Deck
You might be able to use a tool like openFPGALoader to load a bitstream onto your board from macOS.
- openFPGALoader v0.9.0: added support for flashing the Cortex M3 binary of the GW1NSR-4C
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Gowin Programmer not working in Win11
Try openFPGALoader. It works fine in Windows 10 and Linux for me. https://github.com/trabucayre/openFPGALoader
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Software for simulation of Gowin devices and IP?
There's the open source openFPGALoader with explicit support for macOS if i remember correctly, I'm not sure if it supports all the features but it should be a good starting point.
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Programming over remote
u/PCB4lyfe all you need are just the drivers for the USB blaster. To load the bitstream you can use openFPGALoader https://github.com/trabucayre/openFPGALoader
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Help me test if my Basys 3 is working or not
OP, if that doesn't work, and you feel comfortable installing openFPGALoader (https://github.com/trabucayre/openFPGALoader), I can send you the GPIO demo bitstream to put on your board.
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
pcm - Processor Counter Monitor [Moved to: https://github.com/intel/pcm]
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.
picoMIPS - picoMIPS processor doing affine transformation
pcm - Intel® Performance Counter Monitor (Intel® PCM)
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
prjxray - Documenting the Xilinx 7-series bit-stream format.
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
XilinxVirtualCable - Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen