Verilator - Do I need to maintain two testbench suits?

• minimax

  13 194 2.9 Verilog

  Minimax: a Compressed-First, Microcoded RISC-V CPU

I haven't used it on a huge design (I'm usually a VHDL person), but it was a hassle-free replacement for iverilog when regression testing Minimax. Performance is substantially better; compilation times are worse.

• black-parrot

  5 525 8.2 SystemVerilog

  A Linux-capable RISC-V multicore for and by the world

  

Another option is to have a single verilog testbench with clock and reset ports driven by verilator:https://github.com/black-parrot/black-parrot/blob/master/bp_top/test/tb/bp_tethered/test_bp.cpphttps://github.com/black-parrot/black-parrot/blob/master/bp_top/test/tb/bp_tethered/testbench.sv

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

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