axis_udp
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core (by alknvl)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| axis_udp | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 24 | 1,900 | |
| - | 2.2% | |
| 0.0 | 6.3 | |
| about 2 years ago | 29 days ago | |
| Verilog | Verilog | |
| MIT License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
axis_udp
Posts with mentions or reviews of axis_udp.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
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Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.