Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far

• liteeth

  2 191 8.9 Python

  Small footprint and configurable Ethernet core

Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

• verilog-ethernet

  32 1,916 8.8 Verilog

  Verilog Ethernet components for FPGA implementation

Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• ethernet

  1 1 10.0 Verilog

  ethernet experiments on the ECP5-versa (by C-Elegans)

Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

• axis_udp

  1 24 0.0 Verilog

  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

• Verilog_UDP_TCP

  1 5 3.2 Verilog

  Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.

Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

• OS-X-LibMPSSE-SPI

  1 4 0.0 C

The chip also supports SPI and I2C though, but I have not tried that yet as it requires some more fiddling on the PC side regarding drivers (D2XX) and libraries (LibMPSSE). I figured that ethernet would provide the biggest bandwidth improvement, but it is considerably more complicated than the other options.

• hVHDL_gigabit_ethernet

  1 10 7.4 VHDL

  VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.

  

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

Suggest a related project