Verilog_UDP_TCP

Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý. (by ntpt7921)

Verilog_UDP_TCP Alternatives

Similar projects and alternatives to Verilog_UDP_TCP

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better Verilog_UDP_TCP alternative or higher similarity.

Verilog_UDP_TCP reviews and mentions

Posts with mentions or reviews of Verilog_UDP_TCP. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-08-22.
  • Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
    7 projects | /r/FPGA | 22 Aug 2022
    Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

Stats

Basic Verilog_UDP_TCP repo stats
1
5
3.2
over 2 years ago

ntpt7921/Verilog_UDP_TCP is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of Verilog_UDP_TCP is Verilog.


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