axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core (by alknvl)

Axis_udp Alternatives

Similar projects and alternatives to axis_udp

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better axis_udp alternative or higher similarity.

axis_udp reviews and mentions

Posts with mentions or reviews of axis_udp. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-08-22.
  • Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
    7 projects | /r/FPGA | 22 Aug 2022
    Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.

Stats

Basic axis_udp repo stats
1
24
0.0
about 2 years ago

alknvl/axis_udp is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of axis_udp is Verilog.


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