Axis_udp Alternatives
Similar projects and alternatives to axis_udp
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Verilog_UDP_TCP
Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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hVHDL_gigabit_ethernet
VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.
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SaaSHub
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NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better axis_udp alternative or higher similarity.
axis_udp reviews and mentions
Posts with mentions or reviews of axis_udp.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-08-22.
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Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
Stats
Basic axis_udp repo stats
1
24
0.0
about 2 years ago
alknvl/axis_udp is an open source project licensed under MIT License which is an OSI approved license.
The primary programming language of axis_udp is Verilog.
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