liteeth

Small footprint and configurable Ethernet core (by enjoy-digital)

Liteeth Alternatives

Similar projects and alternatives to liteeth

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better liteeth alternative or higher similarity.

liteeth reviews and mentions

Posts with mentions or reviews of liteeth. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-08-22.
  • Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
    7 projects | /r/FPGA | 22 Aug 2022
    Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
  • Ethernet 1G-over RGMII lattice
    2 projects | /r/FPGA | 4 Oct 2021
    You can get some hints from LiteEth’s vendor-free ECP5 RGMII PHY: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/ecp5rgmii.py

Stats

Basic liteeth repo stats
2
191
8.9
16 days ago

enjoy-digital/liteeth is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.

The primary programming language of liteeth is Python.


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