Liteeth Alternatives
Similar projects and alternatives to liteeth
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axis_udp
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
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hVHDL_gigabit_ethernet
VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.
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Verilog_UDP_TCP
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liteeth reviews and mentions
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Questions on sending Ethernet traffic from an ECP5 Versa board, and what I have tried so far
Hungry for more bandwidth (I will need several Mb/s at least for my full-scale setup), I have been looking into using ethernet to get my bits across faster. The plan is to put together a simple UDP stack that can spit out packets to the laptop, with no need to receive any traffic back on the FPGA board. The network link will be direct, using a CAT5E patch cable (no switch), and always connecting with the same remote computer so the IP and MAC addresses can be kept fixed. I have found several spots that have full MAC + PHY cores that should do the job: LiteEth, the Verilog Ethernet cores by Alex Forencich, and a few other projects that do not have much documentation.
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Ethernet 1G-over RGMII lattice
You can get some hints from LiteEth’s vendor-free ECP5 RGMII PHY: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/ecp5rgmii.py
Stats
enjoy-digital/liteeth is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of liteeth is Python.
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