WARP_Core
neorv32
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| WARP_Core | neorv32 | |
|---|---|---|
| 2 | 77 | |
| 7 | 1,423 | |
| - | - | |
| 0.0 | 9.9 | |
| almost 4 years ago | 4 days ago | |
| VHDL | C | |
| - | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
WARP_Core
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Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
verilog-ethernet - Verilog Ethernet components for FPGA implementation
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
picoMIPS - picoMIPS processor doing affine transformation
SpinalHDL - Scala based HDL
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
fiate - Fault Injection Automatic Test Equipment
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set