WARP_Core
satcat5
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| WARP_Core | satcat5 | |
|---|---|---|
| 2 | 25 | |
| 7 | 387 | |
| - | 36.7% | |
| 0.0 | 3.8 | |
| almost 4 years ago | 2 months ago | |
| VHDL | VHDL | |
| - | CERN Open Hardware Licence Version 2 - Weakly Reciprocal |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
WARP_Core
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Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
What are some alternatives?
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
surf - A huge VHDL library for FPGA development
fiate - Fault Injection Automatic Test Equipment
opentitan - OpenTitan: Open source silicon root of trust
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
chisel - Chisel: A Modern Hardware Design Language