WARP_Core
Wilson AXI RISCV Processor Core (by AEW2015)
fiate
Fault Injection Automatic Test Equipment (by byuccl)
Our great sponsors
| WARP_Core | fiate | |
|---|---|---|
| 2 | 4 | |
| 7 | 7 | |
| - | - | |
| 0.0 | 0.0 | |
| almost 4 years ago | over 2 years ago | |
| VHDL | VHDL | |
| - | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
WARP_Core
Posts with mentions or reviews of WARP_Core.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-29.
-
Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
fiate
Posts with mentions or reviews of fiate.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Building xvc_pup device drivers from the source.
Try this: https://github.com/byuccl/fiate/blob/main/host_sw/xvc.py There are other GitHub examples as well. https://github.com/search?q=xilinx+virtual+cable
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Help setting up Xilinx Artix-7 FPGA (RHS Labs Litefury FPGA board)
Here is my Github work with the SQRL Acorn (same design as the litefury): https://github.com/byuccl/fiate
-
SPI flash command set specification
I have that part in a few SQRL acorn FPGAs. Here is my python wrapper for the Xilinx QSPI device. https://github.com/byuccl/fiate/blob/main/host_sw/qspi.py
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing WARP_Core and fiate you can also consider the following projects:
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
litex - Build your hardware, easily!
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images