WARP_Core
Wilson AXI RISCV Processor Core (by AEW2015)
verilog-ethernet
Verilog Ethernet components for FPGA implementation (by alexforencich)
Our great sponsors
WARP_Core | verilog-ethernet | |
---|---|---|
2 | 32 | |
7 | 1,916 | |
- | - | |
0.0 | 8.8 | |
almost 4 years ago | about 2 months ago | |
VHDL | Verilog | |
- | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
WARP_Core
Posts with mentions or reviews of WARP_Core.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-29.
-
Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
verilog-ethernet
Posts with mentions or reviews of verilog-ethernet.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-21.
-
Quartus Tcl Build Script
Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.
-
Using Si5324 as a clock generator on virtex-7 board
For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.
-
DE2-115 Ethernet Network Setup
For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.
-
ROS 2 Humble in AMD KR260 with Yocto
No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.
-
Choice of LFSR When implementing the ARP Cache in a UDP Stack
So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.
-
Preference for Combinational or Sequential design?
I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
-
Verilog Question- Setting a register concurrently twice in always block
I was studying Alex Forencich's FCS verilog and noticed the following always block:
-
LiteX SGMII support
This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet
- Stream data into FPGA from PC
What are some alternatives?
When comparing WARP_Core and verilog-ethernet you can also consider the following projects:
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
corundum - Open source FPGA-based NIC and platform for in-network compute
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
litex - Build your hardware, easily!
SpinalHDL - Scala based HDL
fiate - Fault Injection Automatic Test Equipment
embox - Modular and configurable OS for embedded applications
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
cocotbext-axi - AXI interface modules for Cocotb
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
WARP_Core vs soft_riscv
verilog-ethernet vs corundum
WARP_Core vs SBusFPGA
verilog-ethernet vs litex
WARP_Core vs SpinalHDL
verilog-ethernet vs SpinalHDL
WARP_Core vs fiate
verilog-ethernet vs embox
WARP_Core vs neorv32
verilog-ethernet vs cocotbext-axi
WARP_Core vs satcat5
verilog-ethernet vs satcat5