OpenTimer VS open-register-design-tool

Compare OpenTimer vs open-register-design-tool and see what are their differences.

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems (by OpenTimer)
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design Cpp17 parallel-computing circuit-simulator Verilog electronic-design-automation computer-aided-design eda Cad circuit-simulation circuit-analysis
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open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
systemrdl jspec eda Asic Fpga registers Uvm Systemverilog register-descriptions systemrdl-compiler
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OpenTimer open-register-design-tool
1 2
513 182
1.8% 1.6%
0.0 5.3
11 months ago 9 months ago
Verilog Verilog
GNU General Public License v3.0 or later Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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OpenTimer

Posts with mentions or reviews of OpenTimer. We have used some of these posts to build our list of alternatives and similar projects.

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.
  • Thoughts about SystemRDL ?
    1 project | /r/FPGA | 8 Mar 2021
    I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
  • Auto Generate Header Files
    1 project | /r/FPGA | 28 Jan 2021

What are some alternatives?

When comparing OpenTimer and open-register-design-tool you can also consider the following projects:

ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog

rggen - Code generation tool for control and status registers

hdl - HDL libraries and projects

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

serv - SERV - The SErial RISC-V CPU

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

zipcpu - A small, light weight, RISC CPU soft core

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.

biriscv - 32-bit Superscalar RISC-V CPU

spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

OpenTimer vs ice-chips-verilog open-register-design-tool vs rggen OpenTimer vs hdl open-register-design-tool vs livehd OpenTimer vs serv open-register-design-tool vs gf180mcu-pdk OpenTimer vs zipcpu open-register-design-tool vs PeakRDL-html OpenTimer vs dwsim open-register-design-tool vs biriscv OpenTimer vs spydrnet open-register-design-tool vs openlane