Verilog static-timing-analysis

Open-source Verilog projects categorized as static-timing-analysis
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Topics: Cpp17 Cad parallel-computing eda vlsi
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Verilog static-timing-analysis Projects

  • OpenTimer

    A High-performance Timing Analysis Tool for VLSI Systems

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Index

Project Stars
1 OpenTimer 511

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