OpenTimer Alternatives

Similar projects and alternatives to OpenTimer

• ice-chips-verilog

  4 116 0.9 Verilog OpenTimer VS ice-chips-verilog

  IceChips is a library of all common discrete logic devices in Verilog

• open-register-design-tool

  2 181 5.3 Verilog OpenTimer VS open-register-design-tool

  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• serv

  19 1,234 7.7 Verilog OpenTimer VS serv

  SERV - The SErial RISC-V CPU

• spydrnet

  1 79 6.8 Python OpenTimer VS spydrnet

  A flexible framework for analyzing and transforming FPGA netlists. Official repository.

  

• hdl

  5 1,374 9.0 Verilog OpenTimer VS hdl

  HDL libraries and projects

  

• zipcpu

  13 1,188 6.3 Verilog OpenTimer VS zipcpu

  A small, light weight, RISC CPU soft core

• dwsim

  2 251 9.7 Visual Basic .NET OpenTimer VS dwsim

  DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• openlane

  12 1,174 8.6 Python OpenTimer VS openlane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  

• OpenLANE-Sky130-Physical-Design-Workshop

  1 32 10.0 OpenTimer VS OpenLANE-Sky130-Physical-Design-Workshop

  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130