OpenTimer
ice-chips-verilog
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OpenTimer | ice-chips-verilog | |
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1 | 4 | |
511 | 116 | |
2.2% | - | |
0.0 | 0.9 | |
11 months ago | about 1 year ago | |
Verilog | Verilog | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
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OpenTimer
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Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
ice-chips-verilog
- Software for the arrangement of computer components on breadboards
- Has anyone ever made a z80 out of 7400 series parts?
- I'm really interested in learning more about Verilog but I have no prior coding experience, what's some of the ways a beginner like me can learn more about Verilog and RTL designing in general ?
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Improving my homemade 32-bit RISC-V CPU made only out of discrete logic ICs
If you want to go to the next level I'd suggest recreating the CPU in Verilog and simulating it there. That will let you quickly run testbenches against the virtual version and stress test the logical design itself, which in turn would help rule out electrical problems. Here is a 74-series Verilog simulation library you could use to kickstart a Verilog simulation.
What are some alternatives?
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
hdl - HDL libraries and projects
fritzing-app - Fritzing desktop application
serv - SERV - The SErial RISC-V CPU
LS6502 - 6502 processor implemented in Logisim
zipcpu - A small, light weight, RISC CPU soft core
CPLD-Guide - Complex Programmable Logic Device (CPLD) Guide
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenLANE-Sky130-Physical-Design-Workshop - Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130