OpenTimer
OpenLANE-Sky130-Physical-Design-Workshop
| OpenTimer | OpenLANE-Sky130-Physical-Design-Workshop | |
|---|---|---|
| 1 | 1 | |
| 513 | 32 | |
| 1.8% | - | |
| 0.0 | 10.0 | |
| 11 months ago | over 1 year ago | |
| Verilog | ||
| GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenTimer
-
Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
OpenLANE-Sky130-Physical-Design-Workshop
-
Documentation for the Workshop: Advanced Physical Design using OpenLane/Sky130
Hi, here is a compilation of my notes for the 5 day workshop: Advanced Physical Design using OpenLANE/Sky130 by VSD back in August. The goal of that workshop is to cover the complete RTL2GDSII flow using the open-source flow OpenLane with the SKY130nm PDK.
What are some alternatives?
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
sky90fd-pdk
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
OpenSERDES - Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
hdl - HDL libraries and projects
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
serv - SERV - The SErial RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
zipcpu - A small, light weight, RISC CPU soft core
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.