OpenTimer
open-register-design-tool
OpenTimer | open-register-design-tool | |
---|---|---|
1 | 2 | |
513 | 182 | |
1.8% | 1.6% | |
0.0 | 5.3 | |
11 months ago | 9 months ago | |
Verilog | Verilog | |
GNU General Public License v3.0 or later | Apache License 2.0 |
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OpenTimer
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Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
What are some alternatives?
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
rggen - Code generation tool for control and status registers
hdl - HDL libraries and projects
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
serv - SERV - The SErial RISC-V CPU
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
zipcpu - A small, light weight, RISC CPU soft core
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
biriscv - 32-bit Superscalar RISC-V CPU
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.