OpenTimer
spydrnet
Our great sponsors
| OpenTimer | spydrnet | |
|---|---|---|
| 1 | 1 | |
| 511 | 79 | |
| 2.2% | - | |
| 0.0 | 6.8 | |
| 11 months ago | about 2 months ago | |
| Verilog | Python | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenTimer
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Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
spydrnet
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Is there a minimal HDL?
Here is a python tool to modify netlist / edit files. https://github.com/byuccl/spydrnet
What are some alternatives?
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
difw - Expressive diffeomorphic transformations based on the closed-form integration of continuous piecewise affine velocity functions.
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
naja-verilog - A standalone structural (gate-level) verilog parser
hdl - HDL libraries and projects
stargan2 - StarGAN2 for practice
serv - SERV - The SErial RISC-V CPU
OpenRAM - An open-source static random access memory (SRAM) compiler.
zipcpu - A small, light weight, RISC CPU soft core
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenLANE-Sky130-Physical-Design-Workshop - Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130