Python netlist

Open-source Python projects categorized as netlist
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Topics: eda Fpga Asic Circuit Verilog
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Python netlist Projects

  • spydrnet

    A flexible framework for analyzing and transforming FPGA netlists. Official repository.

  • naja

    Structural Netlist API (and more) for EDA post synthesis flow development

    • Project mention: Naja-Verilog: stand-alone structural (gate-level) parser | /r/FPGA | 2023-10-11

    Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.

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    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Python netlist related posts

  • Show HN: Pylectronics – Reproduce digital electronics in Python

    3 projects | news.ycombinator.com | 29 Aug 2021

Index

Project Stars
1 spydrnet 85
2 naja 42

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