spydrnet
naja-verilog
spydrnet | naja-verilog | |
---|---|---|
1 | 2 | |
85 | 21 | |
- | - | |
6.8 | 7.6 | |
2 months ago | about 1 month ago | |
Python | C++ | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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spydrnet
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Is there a minimal HDL?
Here is a python tool to modify netlist / edit files. https://github.com/byuccl/spydrnet
naja-verilog
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Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
- Show HN: Naja-Verilog – Structural Verilog Parser
What are some alternatives?
difw - Expressive diffeomorphic transformations based on the closed-form integration of continuous piecewise affine velocity functions.
Degate - A modern and open-source cross-platform software for chips reverse engineering.
stargan2 - StarGAN2 for practice
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
verilator - Verilator open-source SystemVerilog simulator and lint system
OpenRAM - An open-source static random access memory (SRAM) compiler.
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
naja - Structural Netlist API (and more) for EDA post synthesis flow development