OpenLANE-Sky130-Physical-Design-Workshop
riscv-cores-list
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10.0 | 1.8 | |
over 1 year ago | about 3 years ago | |
MIT License | - |
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OpenLANE-Sky130-Physical-Design-Workshop
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Documentation for the Workshop: Advanced Physical Design using OpenLane/Sky130
Hi, here is a compilation of my notes for the 5 day workshop: Advanced Physical Design using OpenLANE/Sky130 by VSD back in August. The goal of that workshop is to cover the complete RTL2GDSII flow using the open-source flow OpenLane with the SKY130nm PDK.
riscv-cores-list
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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RISCV IP Cores Overview
That info used to be on GitHub: https://github.com/riscvarchive/riscv-cores-list, it's a shame that the riscv.org site moved away from maintaining the information in a public repository.
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Looking for a RISC-V core for verification
I'm planning to start my Master's thesis on RISC-V verification, so I'm looking for a core that I can use to simulate. I came across this list of cores on github and out of these which would you recommend is ideal for my application. I have only worked on ARM cores before in my internship so the designs were already set up by the company there, but now I am having trouble doing this on my own. I decided to go with the Hummingbirdv2 e203 core as I have experience with verilog, but I am unable to even simulate the test code because of some syntax error. Is there someone who has experience using this core before or can recommend some other core that is straightforward with the setup?
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Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
What are some alternatives?
sky90fd-pdk
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
OpenSERDES - Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
serv - SERV - The SErial RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
riscv - RISC-V CPU Core (RV32IM)
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
Cores-VeeR-EH1 - VeeR EH1 core
riscv-dv - Random instruction generator for RISC-V processor verification