riscv-cores-list
serv
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| riscv-cores-list | serv | |
|---|---|---|
| 4 | 19 | |
| 564 | 1,244 | |
| - | - | |
| 1.8 | 7.7 | |
| about 3 years ago | 17 days ago | |
| Verilog | ||
| - | ISC License |
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riscv-cores-list
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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RISCV IP Cores Overview
That info used to be on GitHub: https://github.com/riscvarchive/riscv-cores-list, it's a shame that the riscv.org site moved away from maintaining the information in a public repository.
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Looking for a RISC-V core for verification
I'm planning to start my Master's thesis on RISC-V verification, so I'm looking for a core that I can use to simulate. I came across this list of cores on github and out of these which would you recommend is ideal for my application. I have only worked on ARM cores before in my internship so the designs were already set up by the company there, but now I am having trouble doing this on my own. I decided to go with the Hummingbirdv2 e203 core as I have experience with verilog, but I am unable to even simulate the test code because of some syntax error. Is there someone who has experience using this core before or can recommend some other core that is straightforward with the setup?
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Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
serv
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know
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Efinix and Xyloni Board - Heard a lot of clients mention them, so took a look.
It will be interesting to see if a Serv will fit with some usable gates left over.
What are some alternatives?
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
IronOS - Open Source Soldering Iron firmware
riscv - RISC-V CPU Core (RV32IM)
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
Cores-VeeR-EH1 - VeeR EH1 core
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
riscv-dv - Random instruction generator for RISC-V processor verification
edalize - An abstraction library for interfacing EDA tools