OpenLANE-Sky130-Physical-Design-Workshop
OpenTimer
| OpenLANE-Sky130-Physical-Design-Workshop | OpenTimer | |
|---|---|---|
| 1 | 1 | |
| 32 | 514 | |
| - | 1.9% | |
| 10.0 | 0.0 | |
| over 1 year ago | 12 months ago | |
| Verilog | ||
| MIT License | GNU General Public License v3.0 or later |
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OpenLANE-Sky130-Physical-Design-Workshop
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Documentation for the Workshop: Advanced Physical Design using OpenLane/Sky130
Hi, here is a compilation of my notes for the 5 day workshop: Advanced Physical Design using OpenLANE/Sky130 by VSD back in August. The goal of that workshop is to cover the complete RTL2GDSII flow using the open-source flow OpenLane with the SKY130nm PDK.
OpenTimer
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Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
What are some alternatives?
sky90fd-pdk
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
OpenSERDES - Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
hdl - HDL libraries and projects
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
zipcpu - A small, light weight, RISC CPU soft core
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
serv - SERV - The SErial RISC-V CPU
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.