Verilog-axi Alternatives

Similar projects and alternatives to verilog-axi

wb2axip

51 431 3.1 Verilog verilog-axi VS wb2axip

Bus bridges and other odds and ends
cocotb

28 1,599 9.7 Python verilog-axi VS cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
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zipcpu

13 1,190 6.3 Verilog verilog-axi VS zipcpu

A small, light weight, RISC CPU soft core
autofpga

9 156 4.3 C++ verilog-axi VS autofpga

A utility for Composing FPGA designs from Peripherals
verilog-axis

7 651 6.2 Python verilog-axi VS verilog-axis

Verilog AXI stream components for FPGA implementation
axidmacheck

2 8 0.0 Verilog verilog-axi VS axidmacheck

AXI DMA Check: A utility to measure DMA speeds in simulation
verilog-axi

2 4 1.3 Verilog verilog-axi VS verilog-axi

Discontinued Verilog AXI components for FPGA implementation (by ZipCPU)
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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better verilog-axi alternative or higher similarity.

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verilog-axi reviews and mentions

Posts with mentions or reviews of verilog-axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-07.

awready and wready set high in master without salve value · Issue #57 · alexforencich/verilog-axi
1 project | /r/FPGA | 18 May 2023
Using Xilinx AXI interconnect to connect AXI lite master to AXI lite slaves
1 project | /r/FPGA | 9 Nov 2022

You can also use an AXI lite crossbar like this one: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axil_crossbar.v
OS AXI4 Crossbar with good performance
4 projects | /r/FPGA | 7 Mar 2022

does anybody knows some sort of AXI4 Crossbar or maybe even an Interconnect with good performance in terms of latency? If I have something like the following scenario, the idea is that M1 txns must have very low access latency in the sense of making the CPU capable of processing at least one instruction per cc. For M2 it's fine to take more time, but what I'm observing is that with this solution for instance, I cannot achieve constant fetching from the CPU, there's always a 1 cc delay between req/resp what hits bad my IPC. Also, S1 cannot be tightly coupled to the CPU because sometimes M2 might require to also fetch from IRAM/ROM. Is it better to switch to another protocol to achieve such good performance latency? if so, what open source available solution can have interesting perf. num, wishbone / AHB?
Hey Xilinx users, let me have it...
4 projects | /r/FPGA | 13 Aug 2021

You can also look at some of my code, which is all MIT licensed: https://github.com/alexforencich/verilog-axi
BRAM to AXI Stream in Xilinx Devices
1 project | /r/FPGA | 30 Jul 2021

AXI DMA, or the datamover core that the AXI DMA core uses internally, depending on your use case. I also have an open source AXI DMA module that's comparable to the Xilinx datamover core here: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axi_dma.v
Converting an FPGA design to ASIC
3 projects | /r/chipdesign | 19 Jul 2021

Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
Fast, open-source RTL IPs for fixed & floating-point multiplication, accumulation & conversion
2 projects | /r/FPGA | 17 Jul 2021

I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.
Assigning values to Verilog parameters from Cocotb?
2 projects | /r/FPGA | 14 Mar 2021

Thanks for the reply! I ran a particular testbench from your repository but when I placed print statements(print(tb.dut.S_DATA_WIDTH.value) in each test (run_test_write,run_test_read) , I found that it prints out the default parameter value (32) every time.
Can someone please explain to me the basic parts of a Cocotb testbench?
2 projects | /r/FPGA | 3 Mar 2021

Here's one of my cocotb testbenches for reference: https://github.com/alexforencich/verilog-axi/blob/master/tb/axi_adapter/test_axi_adapter.py .
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