Fast, open-source RTL IPs for fixed & floating-point multiplication, accumulation & conversion

• verilog-axi

  2 4 1.3 Verilog

  Discontinued Verilog AXI components for FPGA implementation (by ZipCPU)

I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.

• verilog-axi

  9 1,257 3.0 Verilog

  Verilog AXI components for FPGA implementation

I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.

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