Verilog-axi Alternatives
Similar projects and alternatives to verilog-axi
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InfluxDB
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NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better verilog-axi alternative or higher similarity.
verilog-axi reviews and mentions
Posts with mentions or reviews of verilog-axi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-19.
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Converting an FPGA design to ASIC
Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
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Fast, open-source RTL IPs for fixed & floating-point multiplication, accumulation & conversion
I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.
Stats
Basic verilog-axi repo stats
2
4
1.3
over 3 years ago
ZipCPU/verilog-axi is an open source project licensed under MIT License which is an OSI approved license.
The primary programming language of verilog-axi is Verilog.
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