Converting an FPGA design to ASIC

• verilog-axi

  9 1,257 3.0 Verilog

  Verilog AXI components for FPGA implementation

Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.

• verilog-axi

  2 4 1.3 Verilog

  Discontinued Verilog AXI components for FPGA implementation (by ZipCPU)

Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.

• InfluxDB

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• verilog-axis

  7 656 6.2 Python

  Verilog AXI stream components for FPGA implementation

Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.

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