Verilog-axis Alternatives

Similar projects and alternatives to verilog-axis

verilog-axi

9 1,252 3.0 Verilog verilog-axis VS verilog-axi

Verilog AXI components for FPGA implementation
verilog-axi

2 4 1.3 Verilog verilog-axis VS verilog-axi

Discontinued Verilog AXI components for FPGA implementation (by ZipCPU)
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find_first_set

1 1 0.0 Verilog verilog-axis VS find_first_set

Find first set operation in Verilog-2001 with logarithmic complexity.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better verilog-axis alternative or higher similarity.

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verilog-axis reviews and mentions

Posts with mentions or reviews of verilog-axis. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-09-19.

VIO core automation
1 project | /r/FPGA | 30 May 2023
Constraints tied to a single module?
1 project | /r/FPGA | 20 Mar 2023

Another alternative is to use a Tcl script with a foreach, like it's done here: https://github.com/alexforencich/verilog-axis/blob/master/syn/vivado/sync_reset.tcl That file can be added the the list of constraint files in Vivado
Any cons of replacing AXI-Stream Xilinx IPs with open-source (alexforencich) IPs
1 project | /r/FPGA | 26 Sep 2021

I'm grateful to find these open-source RTL IPs of u/alexforencich [AXIS modules: repo]. And they seem like a straightforward replacement to the following Xilinx IPs.
How to compute log2 of non-constant logic variable?
2 projects | /r/FPGA | 19 Sep 2021

Also FYI some FPGA tools have issues with recursive modules. This style can be unrolled, though. See https://github.com/alexforencich/verilog-axis/blob/master/rtl/priority_encoder.v
Converting an FPGA design to ASIC
3 projects | /r/chipdesign | 19 Jul 2021

Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
Looking for feedback on a simple parameterized bus module (verilog) I created to make it easier for me to build 8bit CPU designs
1 project | /r/FPGA | 16 Apr 2021
Can an AXI stream FIFO IP remove bubbles from the input stream?
1 project | /r/FPGA | 2 Mar 2021
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alexforencich/verilog-axis is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of verilog-axis is Python.

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Verilog-axis Alternatives

Similar projects and alternatives to verilog-axis

verilog-axi

verilog-axi

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find_first_set

verilog-axis reviews and mentions

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