Using Xilinx AXI interconnect to connect AXI lite master to AXI lite slaves

• verilog-axi

  9 1,257 3.0 Verilog

  Verilog AXI components for FPGA implementation

You can also use an AXI lite crossbar like this one: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axil_crossbar.v

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

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