Assigning values to Verilog parameters from Cocotb?

• cocotb

  28 1,607 9.7 Python

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  

I could see such parameters being modified in only one example from the documentation but they seemed to have assigned some fixed values in the Makefile itself and change the Makefile manually from test to test.

• verilog-axi

  9 1,257 3.0 Verilog

  Verilog AXI components for FPGA implementation

Thanks for the reply! I ran a particular testbench from your repository but when I placed print statements(print(tb.dut.S_DATA_WIDTH.value) in each test (run_test_write,run_test_read) , I found that it prints out the default parameter value (32) every time.

• InfluxDB

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  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

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