upduino-projects
Various VHDL projects I've worked on for the Upduino v2.0 and v3.0 (by nobodywasishere)
neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
| upduino-projects | neorv32 | |
|---|---|---|
| 3 | 77 | |
| 6 | 1,423 | |
| - | - | |
| 0.0 | 9.9 | |
| over 1 year ago | 8 days ago | |
| VHDL | C | |
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
upduino-projects
Posts with mentions or reviews of upduino-projects.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-24.
- Does any one knows the vhdl code for (7,4) hamming code decoder?
- Using HOSC_CORE (Lattice Radiant, Ice40up5k, Synplify Pro, VHDL)
-
https://np.reddit.com/r/FPGA/comments/mro9hr/using_hosc_core_lattice_radiant_ice40up5k/gvsk3vg/
That'll give you the 48MHz clk. In the open source toolchain, you'd just change HSOSC to SB_HFOSC. More information about how to use the open source toolchain for VHDL (ghdl + yosys + icestorm + nextpnr) can be found in a few repos: - https://github.com/nobodywasishere/upduino-projects - https://github.com/controversial/es4 - https://github.com/YosysHQ/fpga-toolchain
neorv32
Posts with mentions or reviews of neorv32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
-
Recommendations for RISC-V on FPGA
How about NEORV32?
-
SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
-
RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
-
Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
When comparing upduino-projects and neorv32 you can also consider the following projects:
es4 - Code for Tufts ES4 Intro to Digital Electronics
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
picoMIPS - picoMIPS processor doing affine transformation
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
ghdl - VHDL 2008/93/87 simulator
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
upduino-projects vs es4
neorv32 vs VexRiscv
upduino-projects vs vunit
neorv32 vs linux-on-litex-vexriscv
upduino-projects vs spi-fpga
neorv32 vs picoMIPS
upduino-projects vs fpga-toolchain
neorv32 vs chipyard
upduino-projects vs forth-cpu
neorv32 vs lxp32-cpu
upduino-projects vs ghdl
neorv32 vs fpga-zynq