https://np.reddit.com/r/FPGA/comments/mro9hr/using_hosc_core_lattice_radiant_ice40up5k/gvsk3vg/

• upduino-projects

  3 6 0.0 VHDL

  Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

That'll give you the 48MHz clk. In the open source toolchain, you'd just change HSOSC to SB_HFOSC. More information about how to use the open source toolchain for VHDL (ghdl + yosys + icestorm + nextpnr) can be found in a few repos: - https://github.com/nobodywasishere/upduino-projects - https://github.com/controversial/es4 - https://github.com/YosysHQ/fpga-toolchain

• es4

  2 2 0.0 VHDL

  Code for Tufts ES4 Intro to Digital Electronics

That'll give you the 48MHz clk. In the open source toolchain, you'd just change HSOSC to SB_HFOSC. More information about how to use the open source toolchain for VHDL (ghdl + yosys + icestorm + nextpnr) can be found in a few repos: - https://github.com/nobodywasishere/upduino-projects - https://github.com/controversial/es4 - https://github.com/YosysHQ/fpga-toolchain

• InfluxDB

  www.influxdata.com featured

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• fpga-toolchain

  4 255 4.4 C

  Discontinued Multi-platform nightly builds of open source FPGA tools

  

That'll give you the 48MHz clk. In the open source toolchain, you'd just change HSOSC to SB_HFOSC. More information about how to use the open source toolchain for VHDL (ghdl + yosys + icestorm + nextpnr) can be found in a few repos: - https://github.com/nobodywasishere/upduino-projects - https://github.com/controversial/es4 - https://github.com/YosysHQ/fpga-toolchain

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