riscv
cpu11
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riscv | cpu11 | |
---|---|---|
1 | 2 | |
694 | 130 | |
- | - | |
0.6 | 5.9 | |
over 1 year ago | 19 days ago | |
Verilog | Verilog | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv
We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.
cpu11
We haven't tracked posts mentioning cpu11 yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
zipcpu - A small, light weight, RISC CPU soft core
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
uhd - The USRP™ Hardware Driver Repository
ice40_power - Power analysis of the ICE40UP5K-SG48 devices
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
PDP-11 - A collection of PDP-11 related files
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA