cpu11
openlane
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| cpu11 | openlane | |
|---|---|---|
| 2 | 12 | |
| 146 | 1,168 | |
| - | 4.3% | |
| 5.3 | 8.6 | |
| 4 months ago | 10 days ago | |
| Verilog | Python | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
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cpu11
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Tracking mentions began in Dec 2020.
openlane
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[D][P] Represent Analog Circuits as Graphs
I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
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VLSI Tools
OpenLane
- Compiling Code into Silicon
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Kickstarting IC design
And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
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How are modern processors and their architecture designed?
For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
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Project Ideas for Uni
Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
What are some alternatives?
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
rocket-chip - Rocket Chip Generator
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
riscv - RISC-V CPU Core (RV32IM)
opentitan - OpenTitan: Open source silicon root of trust
sv2v - SystemVerilog to Verilog conversion
zerosoc - Demo SoC for SiliconCompiler.
Verilog.jl - Verilog for Julia
Slime-Simulation
OpenROAD-flow-scripts - OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/